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article · 2007

Characterization and modeling methodology for IC’s ESD susceptibility at system level using VF-TLP tester

This paper presents various injection methods aimed at predicting the susceptibility of integrated circuits against electrostatic discharge (ESD) stresses. A...

10 citationsDOI: https://doi.org/10.1109/eosesd.2007.4401767
Characterization and modeling methodology for IC’s ESD susceptibility at system level using VF-TLP tester