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article · 2003

Reusable embedded debugger for 32 bit RISC processor using the JTAG boundary scan architecture

The traditional debug tools for chip tests and software developments need huge investment and plenty of time. These problems can be overcome by an embedded d...

10 citationsDOI: https://doi.org/10.1109/apasic.2002.1031569
Reusable embedded debugger for 32 bit RISC processor using the JTAG boundary scan architecture